Using GPCE Principles for Hardware Systems and Accelerators (bridging the gap to HW design)

Rishiyur S. Nikhil, Ph.D. CTO, Bluespec Inc.

Moore's Law has precipitated a crisis in the creation of hardware systems (ASICs and FPGAs)--how to design such enormously complex concurrent systems quickly, reliably and affordably? At the same time, portable devices, the energy crisis, and high performance computing present a related challenge--how to move complex and high-performance algorithms from software into hardware (for more speed and/or energy efficiency)?

In this talk I will start with a brief technical introduction to BSV, a language that directly addresses these concerns. It uses ideas from Guarded Atomic Actions (cf. Term Rewriting Systems, TLA+, Unity, and EventB) to address complex concurrency with scalability. It borrows from Haskell (types, type classes, higher-order functions) for robustness and powerful program generation (a.k.a. "static elaboration" to HW designers). And it is fully synthesizable (compilable) into high-quality RTL (Verilog/VHDL). I will then describe some of the remarkable projects that BSV has enabled in industry and academia today.

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